L6450 28 channel ink jet driver advance data 40v dmos output breakdown two decoder options are included precise output energy esd output protection with clamp- ing diodes very low quiescent current plcc44 or pqfp44 (10 x 10mm) description the L6450 is realized in multipower bcd tech- nology which combines isolated dmos power transistors with cmos and bipolar circuits on the same ic. by using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible perform- ances. intended to be used in ink jet printer applications as 4 to 28 (2 x 14) or 3 to 28 (4 x 7) lines select- able decoder/driver, the L6450 device driver has the advantages of low power cmos inputs and logic, with 28 high current and high voltage dmos outputs capable of sustaining a maximum of 40v. on system power up the output drivers are locked out using the chip enable function; four enable in- puts are available for the different driver banks. an internal power-on system is implemented in order to avoid wrong output commutation during the supply voltage transients. using a mask option during manufacturing allows a different decoding. control of the energy delivered to the print head is made by means of a special circuitry. all driver outputs are capable of withdstanding a contact discharge of 8kv with the ic biased. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change withou t notice. march 1994 block diagram (case of 4 bit) pqfp44 plcc44 multipower bcd techno logy 1/9
block diagram (case of 3 bit) pqfp44 pin connection (top view) L6450 2/9
plcc44 pin connection (top view) pin functions name function v dd 5v logic supply. gnd logic and power ground. out0 to out27 dmos outputs. clamp this pins have to be connected to the power supply voltage of the head resistors, each of the output dmos have their drain connected with the anode of a protection diode, all the catodes of the protection diodes are collected to the pins clamp. if the clamp pins are not connected to the power, the device is not supplied. ina, inb, inc, ind decoder inputs. the input ind shares the pin with the other input com3, the two different functions are selected by the pin bench. com1, com2, com3, com4 a low logic input on this pins enable the outputs selected by the decoder inputs according to the logic level of the pin bench. the input com3 shares the pin with the other input ind, the two different functions are selected by the pin bench. chip enable a logic high enable the chip. thermal data symbol parameter pqfp44 plcc44 unit r th j-amb thermal resistance junction-ambient max. 55 (*) 65 (*) c/w (*) dev ice mounted on pcb. L6450 3/9
d.c. electrical characteristics at t amb = 25 c, v dd = 5v, v clamp = 18v (unless otherwise specified). symbol parameter test condition min. typ. max. unit v dd logic supply voltage 4.75 5 5.25 v v clamp clamping voltage 9 38 v v il low level input voltage 1.2 v v ih high level input current v dd -1.2 v i ll low level input current v in = v il -200 m a i lh high level input current v in = v ih 10 m a i dd logic supply current (indipendent from the output conditions) 5ma v out output saturation voltage tj 25 c d.c. 0.4a tj 25 c d.c. 0.5a tj 90 c d.c. 0.4a tj 90 c d.c. 0.5a 0.9 1.1 1.4 1.7 v v v v d v ce output saturation absolute voltage variation around the typ. values for extended temperature ranges tj = 25 c to 90 c d.c.: 0.4a tj = 25 c to 90 c d.c.: 0.5a 0.2 0.25 v v r ds on 2.2 w absolute maximum ratings symbol parameter value unit v out output voltage 40 v v clamp output clamping voltage 40 v i out output continuous current 0.8 a i peak output peak current (with duty cycle = 10% t on = 4 m s) 2 a t j junction temperature 150 c v dd logic supply voltage 7 v v in input voltage range -0.3v to v s +0.3 v t amb operating temperature range 0 to 70 c t stg storage temperature range -55 to 150 c a.c. electrical characteristics at t amb = 25 c, v dd = 5v. symbol signal name parameter test condition min. typ. max. unit t s ina, inb, inc, ind vs comn set - up time 30 ns t h ina, inb, inc, ind vs comn hold time 0 ns t on com1,2,3,4 v s out 0 to n turn - on time i out = 0.5a, r l = 39 w t j = 25 to 90 c 150 ns t off com1,2,3,4 v s out 0 to n turn - off time i out = 0.5a, r l = 39 w t j = 25 to 90 c 150 ns t r rise time 100 ns t f fall time 100 ns t wout output pulse width t win = 3.5 m s r l = 40 w i out = 0.5a - 20 t win + 80 ns d p d maximum allowable variation of the output power transmitted by each driver to the resistive load r l = 39 w v clamp = 18v 4% L6450 4/9
output selection 1)decoder truth table when the bench = high; ind/ com3 = is selected as input decoder ind; com1 = a low input enable the out0 to out13; com2 = a low input enable the out14 to out27 ind inc inb ina (lsb) outputs 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.27 1.26 2.25 3.24 4.23 5.22 6.21 7.20 8.19 9.18 10.17 11.16 12.15 13.14 all off all off 2)decoder truth table when the bench = low; ind/ com3 = is selected as com3 com1: a low input enable the out0 to out6 com2: a low input enable the out7 to out13 com3: a low input enable the out14 to out20 com4: a low input enable the out21 to out27 inc inb ina (lsb) outputs 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0, 7,27, 20 1, 8, 26, 19 2, 9, 25, 18 3, 10, 24, 17 4, 11, 23, 16 5, 12, 22, 15 6, 13, 21, 14 all off figure 1: timing waveforms L6450 5/9
figure 2: application circuit L6450 6/9
pqfp44 (14 x 14) package mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.0098 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.35 0.50 0.0138 0.0197 c 0.13 0.23 0.005 0.009 d 16.95 17.20 17.45 0.667 0.677 0.687 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 10.00 0.394 e 1.00 0.039 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 10.00 0.394 l 0.65 0.80 0.95 0.025 0.0315 0.0374 l1 1.60 0.063 k 0 (min.), 7 (max.) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e3 d3 e1 e d1 d e 1 k b pqfp44 l l1 0.10mm .004 L6450 7/9
plcc44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 L6450 8/9
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publi cation are subject to change without not ice. this publication sup ersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support dev ices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies aust ralia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united k ingdom - u.s.a. L6450 9/9
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